With rapid development of display techniques, displays show a development trend of high integration and low cost. The Gate Driver on Array (GOA) technique integrates gate switching circuits of a Thin Film Transistor (TFT) on an array substrate of a display panel to form a scan driving to the display panel, so as to leave out wiring space of a bonding area of a gate Integrated Circuit (IC) and a Fan-out area, which can not only reduce product cost in two aspects of both material cost and manufacturing process, but also achieve symmetry on both sides of the display panel and a beautiful design of a narrow border. And such integration technique can also eliminate the need of bonding process in a gate scanning line direction, thus improve productivity and yield.
A GOA circuit is usually composed by a plurality of cascaded shift registers, wherein driving signal output terminals of the shift registers in each stage correspond to one gate line, so that the gate lines are arranged in order along a scanning direction. In general, a scanning time length for each row of gate lines is fixed. Therefore, the GOA circuit described above is not applicable to a display device that needs to adjust the scanning time length for each row of gate lines according to situations. Although different clock control signals can be used to achieve adjustment of the scanning time length, this requires using multiple clock controllers, and for a different scanning time length, the cascade relationship among the shift registers in the GOA circuit is also different, resulting in that it has become more difficult to apply the GOA circuit to the display device that needs to adjust the scanning time length for each row of gate lines according to situations, and production cost of such display device is increased, causing the corresponding display device not competitive.